Nonvolatile memory is well known in the art. The different types of nonvolatile memory include read-only-memory (ROM), electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), NOR flash memory, and NAND flash memory. In current applications such as personal digital assistants, cellular telephones, notebook and laptop computers, voice recorders, global positioning systems, etc., the flash memory has become one of the more popular types of nonvolatile memory. Flash memory has the combined advantages of the high density, small silicon area, and low cost and can be repeatedly programmed and erased with a single low-voltage power supply voltage source.
The NAND and NOR flash memory cell structures use one charge retaining (charge storage or charge trapping) transistor memory cell for storing one bit of data as charge. The storage cell with one bit data is commonly referred to as a single-level cell (SLC). They are respectively referred to as one-bit/one transistor (1b/1T) NAND cell or NOR cell, storing a single-level programmed data in the cell. In addition to storing data as a single-level program cell having two voltage thresholds (Vt0 and Vt1), both 1T NAND and NOR flash memory cells are capable of storing at least two bits per cell or two bits/one transistor (2b/1T) with four multi-level threshold voltages (Vt0, Vt1, Vt2 and Vt3) in one physical cell. The storage cell with the multi-level threshold voltages of the one transistor NAND or NOR flash memory cells is referred to as a multiple level cell (MLC).
Currently, the highest-density of a single-chip double polycrystalline silicon gate NAND flash memory chip is 64 Gb. In contrast, a double polycrystalline silicon gate NOR flash memory chip has a density of 2 Gb. The big gap between NAND and NOR flash memory densities is a result of the superior scalability of a NAND flash memory cell over a NOR flash memory cell. A NOR flash memory cell requires 5.0V drain-to-source (Vds) to maintain a high-current Channel-Hot-Electron (CHE) injection programming process. Due to this CHE scheme, the cell's channel length is very difficult to be scaled down. Alternately, a NAND flash memory cell requires 0V between the drain to the source for a low-current Fowler-Nordheim (FN) channel tunneling program process. The above results in the one-bit/one transistor NAND flash memory cell size being only one half that of a one-bit/one transistor NOR flash memory cell, and therefore higher memory density. As a result, it is always desirable to use the NAND process to manufacture NOR flash memory.
U.S. Pat. No. 6,212,102 of Infineon discloses a two transistor (2T) NOR flash memory. In the flash memory, a high voltage is also required across the drain and source region during FN-edge programming, and therefore a longer channel length is needed to prevent the punch through effect. This causes a physical limitation on how small the cell can be made and in turn limits the use of the cell in ultra high integrated levels of the flash memory below 0.18 um technology. Furthermore, the negative FN-edge programming causes device oxide degradation because the electron-hole pairs at the biased drain to triple P-well (TPW) junction are accelerated by the voltage difference between the drain and the source. The more holes are trapped in the tunneling oxide and the less program and erase endurance cycles can be achieved.
U.S. Pat. Nos. 6,307,781 and 6,628,544 of Infineon provide some improvement over the previous NOR flash memory with uniform channel erase and channel program operations by connecting the common source together in the array of the flash memory. With the connected common source, the gate of the access device has to be applied with the most negative voltage, e.g. −3V, to turn off the path to different bit lines through the common source line. Because of this biased condition during program operation, the program inhibit voltage, i.e., 3V-4V is supposed to isolate the access device. However, the drain induced leakage current may occur if the channel length is scaled down in the cell. Therefore, the flash memory still encounters the scaling issue and ends up with a large memory cell size.
In another NOR flash memory, U.S. Pat. No. 6,980,472 of Philips, both source injection program and FN channel program are disclosed. For the FN channel program, it is similar to the one used in Infineon's patent. The channel length of the access device can not be shortened because of the drain induced leakage current to the common source line when the program inhibit voltage is applied across the drain and the source. Similarly, for the source injection program scheme, the access device needs longer channel length to prevent the punch through effect. In addition, compared to FN channel program, it needs more program current because of the hot-electron generation.